1. Introduction to Computer Organization
Computer Organization refers to the structural relationships and operational units that make up a computer system—how hardware components are connected and interact to execute instructions. It focuses on the "how" of computing: how data flows, how instructions are fetched and executed, and how components coordinate.
🔍 Note:
- Computer Architecture = What the system does (instruction set, design specs).
- Computer Organization = How it does it (hardware implementation, data paths).
2. Basic Structure of a Computer System
A computer is organized around five core functional units that work together:
- Input Unit
- Output Unit
- Memory Unit
- Arithmetic and Logic Unit (ALU)
- Control Unit (CU)
These units are interconnected via buses and managed by the Control Unit.
3. Core Functional Units
🔹 1. Input Unit
- Function: Accepts data and instructions from the external world.
- Devices: Keyboard, mouse, scanner, microphone, sensors.
- Role in Organization: Converts user input into binary form for the CPU.
🔹 2. Output Unit
- Function: Presents processed results to the user.
- Devices: Monitor, printer, speakers, projectors.
- Role: Converts binary data from memory/CPU into human-readable form.
🔹 3. Memory Unit (Main/Primary Memory)
- Function: Stores programs, data, and intermediate results during execution.
- Types:
- RAM (Random Access Memory): Volatile, read/write.
- ROM (Read-Only Memory): Non-volatile, stores boot instructions (e.g., BIOS).
- Key Feature: Directly accessible by the CPU.
🔹 4. Arithmetic and Logic Unit (ALU)
- Function: Performs all arithmetic (add, subtract, multiply) and logical (AND, OR, NOT, comparisons) operations.
- Output: Results sent to memory or registers.
- Speed: Operations completed in nanoseconds.
🔹 5. Control Unit (CU)
- Function: The "traffic controller" of the computer.
- Responsibilities:
- Fetches instructions from memory.
- Decodes them.
- Coordinates all operations (ALU, memory, I/O).
- Generates control signals for data movement.
- Does NOT process data—only directs processing.
💡 Together, ALU + CU = CPU
4. The Central Processing Unit (CPU)
The CPU is the brain of the computer, integrating the ALU and Control Unit.
Key Internal Components:
- Registers: Small, ultra-fast storage locations inside the CPU.
- Program Counter (PC): Holds address of next instruction.
- Instruction Register (IR): Holds current instruction being executed.
- Accumulator (ACC): Stores ALU results temporarily.
- Cache Memory: High-speed memory (L1, L2, L3) between CPU and RAM to reduce access time.
CPU Operation Cycle (Fetch-Decode-Execute):
- Fetch: CU retrieves instruction from memory (address in PC).
- Decode: CU interprets the instruction.
- Execute: ALU performs operation; result stored in register/memory.
- Update PC: Move to next instruction.
⚙️ This cycle repeats billions of times per second (clock speed = GHz).
5. Memory Hierarchy
Computers use a hierarchical memory system to balance speed, cost, and capacity:
Fastest & Most Expensive → Slowest & Cheapest
↓
Registers → Cache (L1/L2/L3) → RAM → Secondary Storage (SSD/HDD) → Tertiary (Tape/Cloud)
| Level | Speed | Volatility | Capacity | Example |
|---|---|---|---|---|
| Registers | Nanoseconds | Volatile | Very Low | CPU registers |
| Cache | Few ns | Volatile | Low | L1: 32–64 KB/core |
| Main Memory | 10–100 ns | Volatile | Medium | RAM (8–64 GB) |
| Secondary | Milliseconds | Non-volatile | High | SSD (512 GB–2 TB) |
| Tertiary | Seconds | Non-volatile | Very High | Cloud storage |
✅ Principle: Frequently used data kept in faster memory (Locality of Reference).
6. System Bus Architecture
Buses are communication pathways that connect CPU, memory, and I/O devices.
Three Main Types of Buses:
| Bus Type | Width | Function |
|---|---|---|
| Data Bus | 8–64+ bits | Transfers data between CPU, memory, I/O |
| Address Bus | 16–64 bits | Carries memory addresses (unidirectional: CPU → memory) |
| Control Bus | Varies | Sends control signals (e.g., READ, WRITE, RESET) |
🔌 Bus Width determines how much data can be transferred at once (e.g., 64-bit bus = 8 bytes per cycle).
7. Von Neumann vs. Harvard Architecture
🔸 Von Neumann Architecture (Most Common)
- Single memory for both instructions and data.
- Single bus for data and instructions → Von Neumann Bottleneck (limits speed).
- Used in: PCs, laptops, servers.
Diagram:
[CPU] ↔ [Memory (Instructions + Data)] ↔ [I/O]
🔸 Harvard Architecture
- Separate memories for instructions and data.
- Separate buses → faster parallel access.
- Used in: Microcontrollers, DSPs, embedded systems (e.g., Arduino, PIC).
Diagram:
[CPU] ↔ [Instruction Memory]
[CPU] ↔ [Data Memory]
✅ Modern CPUs use a modified Harvard architecture (separate caches for instructions/data, but unified main memory).
8. Block Diagram & Data Flow
+-------------+ +---------------------+
| INPUT | | OUTPUT |
| DEVICES | | DEVICES |
+------+------+ +----------+----------+
| ^
| |
v |
+------+------+ +--------+--------+
| | | |
| MEMORY |<------>| CPU |
| (RAM/ROM) | | (ALU + Control) |
| | | |
+------+------+ +-----------------+
^
|
+------+------+
| SECONDARY |
| STORAGE |
| (HDD, SSD) |
+-------------+
Data Flow Example:
- User types "2 + 3" → Input Unit sends to Memory.
- CU fetches instruction "ADD" → decodes → sends operands to ALU.
- ALU computes 5 → result stored in Memory.
- CU directs Output Unit to display "5".
9. Key Concepts & Terminology
- Stored Program Concept: Instructions and data stored in same memory (Von Neumann).
- Clock Cycle: Basic time unit for CPU operations.
- Throughput: Number of instructions executed per second.
- Latency: Time delay between request and response.
- I/O Controllers: Manage communication between CPU and peripherals (e.g., USB controller).
- Interrupts: Signals from I/O devices to CPU (e.g., key press), allowing asynchronous operation.
10. Glossary
- ALU: Arithmetic Logic Unit – performs calculations.
- CU: Control Unit – manages instruction execution.
- Bus: Communication channel between components.
- Register: High-speed CPU storage.
- Memory Hierarchy: Layered memory system optimizing speed/cost.
- Von Neumann Architecture: Unified memory for code and data.
- Harvard Architecture: Separate memories for code and data.
- Fetch-Decode-Execute: Core CPU operation cycle.